1. Field
This disclosure relates generally to testing of processor integrated circuits, and more specifically, to techniques for efficiently introducing instructions and data for core functional pattern tests.
2. Related Art
Modern multi-core processor designs can include numerous processor cores operating at high frequencies. Complex on-chip interconnect micro-architectures have been developed, in part, to achieve high bandwidth and/or low latencies in communications amongst such processor cores, memory and other devices in system on chip (SoC) designs. Unfortunately, compared to the operating frequencies, data transfer bandwidths and latencies achievable using such technologies, input/output (I/O) interfaces available or dedicated to test are typically slow and exhibit low bandwidth and high latency. This performance gap can make conventional external-tester-driven test strategies awkward and/or ineffective for at-speed testing of complex SoC and multi-core processor designs.
As a result, embedded software-based self-testing strategies have gained popularity. These strategies generally assume that processors or programmable cores can first be self-tested by running thereon synthesized test programs that achieve high fault coverage. Next, a processor or programmable core is itself used as a functional pattern generator and response analyzer to test on-chip interconnects, interfaces amongst cores, and even other cores including digital, mixed-signal or analog components of an SoC design. This strategy is sometimes referred to as functional pattern testing.
Unfortunately, just as the performance gap between processor cores and interconnects (on the one hand) and I/O interfaces available or dedicated to test (on the other) complicates conventional external-tester-driven test, such performance gaps can likewise complicate the process of introducing (e.g., through scan logic or other I/O facility) the very test programs and related data that define core functional pattern tests. As a result, the process of introducing instructions and data patterns for the core functional pattern tests can itself be quite time consuming. Worse still, it is generally desirable to generate functional patterns for each processor or core. Accordingly, challenges that are significant even for a single processor or core tend to scale dramatically when the introduction of instructions and data patterns for a multiplicity of processors or cores is considered.
Conventional techniques whereby individual instructions and data for functional patterns are scanned directly from I/O or test interfaces to targets in memory may be undesirable or just plain inadequate. Improved techniques are desired.
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